1. Field of the Invention
The present invention relates to a master slice used in a gate array type LSI, and more particularly to a CMOS master slice in which a set of basic cells each comprising p-channel MOS transistors and n-channel MOS transistors are, arranged regularly.
2. Related Background Art
FIG. 1 shows a plan view of a basic cell used in a prior art gate spread type CMOS master slice. A basic cell 1 comprises a p-channel region 2 and an n-channel region 3. In the p-channel region 2, two p-channel large MOS transistors shown by gates 4 and 5, and two p-channel small MOS transistors shown by gates 6 and 7 are formed. In the n-channel region 3, two n-channel large MOS transistors shown by gates 8 and 9, and two n-channel small MOS transistors shown by gates 10 and 11 are formed. Numeral 12 denotes a p-well region formed on an n-type semiconductor substrate, and numerals 13-17 denote wiring tracks along the width of the gates.
At the beginning of the development of the gate array, it was a general practice that the gate widths of all MOS transistors in a basic cell are equal. However, since it is frequently advantageous in circuit performance the gate width is selectable depending on an application, MOS transistors having different gate widths are incorporated in one basic cell in a recent device.
In the basic cell, the basic MOS transistors 4, 5, 8 and 9 having the wider gate width are used as latch transistors, and n-channel additional MOS transistors 10 and 11 having the narrower gate width are used as path transistors to form one unit of a high performance SRAM memory circuit having a short access time.
However, where transistors having different gate widths are incorporated in one basic cell, wasteful spaces rae created on both sides of each of the pads of the narrow gate width transistors 6, 7, 10 and 11 and an integration efficiency is low.